`timescale 1 ns/1 ns
`define dil 2
module arm_processor(
          clk,
          cpu_en,
			 rst,
			 fiq,
          irq,         
			 ram_addr,
          ram_cen,
          ram_flag,
          ram_wdata,
          ram_wen,
          ram_abort,
          ram_rdata,
          rom_abort,
          rom_data,          
          rom_addr,
          rom_en, 
			 cpu_restart
        ); 


input            clk;
input            cpu_en;
input            cpu_restart;
input            fiq;
input            irq;
input            ram_abort;
input  [31:0]     ram_rdata;
input            rom_abort;
input  [31:0]     rom_data;
input            rst;


output [31:0]     ram_addr;
output           ram_cen;
output [3:0]     ram_flag;
output [31:0]     ram_wdata;
output           ram_wen;
output [31:0]     rom_addr;
output           rom_en;


/******************************************************/
//register definition area
/******************************************************/
reg              add_c;
reg    [1:0]     add_extra_num;
reg              adder_a_inv;
reg              adder_b_inv;
reg    [3:0]     cha_fmt;
reg              cd_abort;
reg              cd_cen;
reg              cd_cha_flag;
reg              cd_flag;
reg    [31:0]     cd_rm;
reg    [31:0]     cd_rs;
reg    [3:0]     cd_rt_num;
reg              cd_to_flag;
reg              cd_und;
reg              cond_satisfy;
reg              cpsr_dc;
reg              cpsr_dc_in;
reg              cpsr_df;
reg              cpsr_di;
reg    [4:0]     cpsr_dm;
reg              cpsr_dn;
reg              cpsr_dn_in;
reg              cpsr_dv;
reg              cpsr_dv_in;
reg              cpsr_dz;
reg              cpsr_dz_in;
reg              dp0_rrx_sdvig;
reg              dp1_lsl_more;
reg              dp1_sdvig_zero;
reg    [31:0]     dp_vykhod;
reg              fiq_flag;
reg    [31:0]     poluchat_rn;
reg    [31:0]     go_data;
reg    [5:0]     go_fmt;
reg    [3:0]     go_n;
reg              go_deystvit;
reg              irq_flag;
reg              zagru_m_change;
reg    [3:0]     zagru_m_num;
reg    [3:0]     zagru_m_vybirat;
reg              zagru_m_deystvit;
reg    [4:0]     m_after;
reg              multl_extra_num;
reg              multl_z;
reg    [31:0]     rf;
reg    [31:0]     rfx;
reg    [31:0]     rt;
reg    [31:0]     ra;
reg    [31:0]     ra_fiq;
reg    [31:0]     ra_usr;
reg    [3:0]     ram_flag;
reg    [31:0]     ram_wdata;
reg    [31:0]     rb;
reg    [31:0]     rb_fiq;
reg    [31:0]     rb_usr;
reg    [31:0]     rc;
reg    [31:0]     rc_fiq;
reg    [31:0]     rc_usr;
reg    [31:0]     rd;
reg    [31:0]     rd_abt;
reg    [31:0]     rd_fiq;
reg    [31:0]     rd_irq;
reg    [31:0]     rd_svc;
reg    [31:0]     rd_und;
reg    [31:0]     rd_usr;
reg    [31:0]     re;
reg    [31:0]     re_abt;
reg    [31:0]     re_fiq;
reg    [31:0]     re_irq;
reg    [31:0]     re_svc;
reg    [31:0]     re_und;
reg    [31:0]     re_usr;
reg    [31:0]     reg_rn;
reg    [31:0]     reg_rs;
reg    [31:0]     vtoroy_operd;
reg    [31:0]     r0;
reg    [31:0]     r1;
reg    [31:0]     r2;
reg    [31:0]     r3;
reg    [31:0]     r4;
reg    [31:0]     r5;
reg    [31:0]     r6;
reg    [31:0]     r7;
reg    [31:0]     r8;
reg    [31:0]     r8_fiq;
reg    [31:0]     r8_usr;
reg    [31:0]     r9;
reg    [31:0]     r9_fiq;
reg    [31:0]     r9_usr;
reg              sdvig_bit;
reg    [6:0]     sdvig_num;
reg    [31:0]     sdvig_word;
reg    [31:0]     sdvig_ans;
reg    [31:0]     sdvig_hi;
reg    [31:0]     sdvig_lw;
reg    [4:0]     sdvig_rt_n;
reg    [10:0]     spsr;
reg    [10:0]     spsr_abt;
reg    [10:0]     spsr_fiq;
reg    [10:0]     spsr_irq;
reg    [10:0]     spsr_svc;
reg    [10:0]     spsr_und;
reg    [4:0]     summa_m;
reg    [31:0]     to_data;
reg    [3:0]     to_n;
reg    [31:0]     command;
reg              command_is_msr;
reg              command_is_mult;
reg              command_is_multl;
reg              command_is_swi;
reg              command_is_swp;
reg              command_is_swpx;
reg              command_flag;
reg              command_is_b;
reg              command_is_bx;
reg              command_is_dp;
reg              command_is_mrs;


reg    [4:0]     command_summa;


/******************************************************/


/******************************************************/
//wire definition area
/******************************************************/
wire   [31:0]     add_a;
wire   [31:0]     add_b;
wire             all_cd;
wire   [31:0]     and_ans;
wire             bit_cy;
wire             bit_ov;
wire   [3:0]     cha_num;
wire             cha_rf_deystvit;
wire             cha_deystvit;
wire   [31:0]     command_addr;
wire             command_is_zagru_m;
wire             command_ok;
wire   [31:0]     cd;
wire             cd_is_b;
wire             cd_is_bx;
wire             cd_is_zagru_m;
wire             cd_is_ldr0;
wire             cd_is_ldr1;
wire             cd_is_ldrh0;
wire             cd_is_ldrh1;
wire             cd_is_ldrsb0;
wire             cd_is_ldrsb1;
wire             cd_is_ldrsh0;
wire             cd_is_ldrsh1;
wire             cd_is_dp;
wire             cd_is_dp0;
wire             cd_is_dp1;
wire             cd_is_dp2;
wire             cd_is_mrs;
wire             cd_is_msr0;
wire             cd_is_msr1;
wire             cd_is_mult;
wire             cd_is_multl;
wire             cd_is_swi;
wire             cd_is_swp;
wire   [3:0]     cd_rm_num;
wire             cd_rm_deystvit;
wire   [3:0]     cd_rn_num;
wire             cd_rn_deystvit;
wire   [3:0]     cd_rnhi_num;
wire             cd_rnhi_deystvit;
wire   [3:0]     cd_rs_num;
wire             cd_rs_deystvit;
wire   [4:0]     cd_summa;
wire   [10:0]     cpsr;
wire   [31:0]     eor_ans;
wire             fiq_en;
wire   [3:0]     poluchat_rn_num;
wire             go_rf_deystvit;
wire             hi_bit;
wire   [1:0]     hi_sredniy;
wire             derzhat_en;
wire             int_all;
wire             irq_en;
wire   [31:0]     zagru_m_data;
wire             zagru_m_rf_deystvit;
wire             zagru_m_usr;
wire   [31:0]     reg_rm;
wire   [31:0]     rf_b;
wire   [63:0]     mult_ans;
wire   [31:0]     or_ans;
wire   [31:0]     ram_addr;
wire             ram_cen;
wire             ram_wen;

wire   [31:0]     rom_addr;
wire             rom_en;
wire   [3:0]     rt_na;
wire   [4:0]     rt_nb;
wire   [4:0]     rt_nc;
wire   [4:0]     rot_numd;
wire   [4:0]     rot_nume;
wire   [3:0]     rt_num;
wire   [63:0]     sdvig_ot;
wire   [31:0]     summa_sredniy;
wire   [31:0]     summa_rn_rm;
wire             to_rf_deystvit;
wire             to_deystvit;
wire             wait_en;


/*Here we gonna determine the rom_data from data pool */

assign all_cd =  cd_is_mrs|cd_is_msr0|cd_is_bx|cd_is_mult|cd_is_multl|cd_is_swp|cd_is_ldrh0|
					  cd_is_ldrh1|cd_is_ldrsb0|cd_is_ldrsb1|cd_is_ldrsh0|cd_is_ldrsh1|cd_is_msr1|
					  cd_is_dp0|cd_is_dp1|cd_is_dp2|cd_is_ldr0|cd_is_ldr1|cd_is_zagru_m|cd_is_b|cd_is_swi;

assign cd_is_swp =  ({cd[27:23],cd[21:20],cd[11:4]}==15'b00010_00_00001001);

assign cd_is_ldr0 =  (cd[27:25]==3'b010);

assign cd_is_ldr1 =  ({cd[27:25],cd[4]}==4'b0110);

assign cd_is_ldrh0 =  ({cd[27:25],cd[22],cd[11:4]}==12'b000_0_00001011);

assign cd_is_ldrh1 =  ({cd[27:25],cd[22],cd[7:4]}==8'b000_1_1011);	

assign cd_is_ldrsb0 =  ({cd[27:25],cd[22],cd[20],cd[11:4]}==13'b000_0_1_00001101);

assign cd_is_ldrsb1 =  ({cd[27:25],cd[22],cd[20],cd[7:4]}==9'b000_1_1_1101);	

assign cd_is_ldrsh0 =  ({cd[27:25],cd[22],cd[20],cd[11:4]}==13'b000_0_1_00001111);

assign cd_is_ldrsh1 =  ({cd[27:25],cd[22],cd[20],cd[7:4]}==9'b000_1_1_1111);

assign cd_is_msr1 =  ({cd[27:23],cd[21:20],cd[18:17],cd[15:12]}==13'b00110_10_00_1111);

assign cd_is_dp2 =  (cd[27:25]==3'b001)&((cd[24:23]!=2'b10)|cd[20]);

assign cd_is_zagru_m =  (cd[27:25]==3'b100);	

assign cd_is_b =  (cd[27:25]==3'b101);

assign cd_is_swi =  (cd[27:24]==4'b1111);					  
					  
assign cd =  rom_data;

assign cd_is_mrs =  ({cd[27:23],cd[21:16],cd[11:0]}==23'b00010_001111_000000000000);

assign cd_is_msr0 =  ({cd[27:23],cd[21:20],cd[18:17],cd[15:4]}==21'b00010_10_00_111100000000);

assign cd_is_dp0 =  ({cd[27:25],cd[4]}==4'b0000)&((cd[24:23]!=2'b10)|cd[20]);

assign cd_is_bx =  (cd[27:4]==24'b0001_0010_1111_1111_1111_0001);

assign cd_is_dp1 =  ({cd[27:25],cd[7],cd[4]}==5'b00001) & ((cd[24:23]!=2'b10)|cd[20]);	

assign cd_is_mult =  ({cd[27:22],cd[7:4]}==10'b000000_1001);

assign cd_is_multl =  ({cd[27:23],cd[7:4]}==9'b00001_1001);	



// Rm and Rs sdviging place

always @ ( * )
case ( cd[11:8] )
4'h0 : cd_rs =  r0;
4'h1 : cd_rs =  r1;	
4'h2 : cd_rs =  r2;
4'h3 : cd_rs =  r3;
4'h4 : cd_rs =  r4;
4'h5 : cd_rs =  r5;	
4'h6 : cd_rs =  r6;
4'h7 : cd_rs =  r7;	
4'h8 : cd_rs =  r8;
4'h9 : cd_rs =  r9;	
4'ha : cd_rs =  ra;
4'hb : cd_rs =  rb;
4'hc : cd_rs =  rc;
4'hd : cd_rs =  rd;	
4'he : cd_rs =  re;
4'hf : cd_rs =  32'b0;
endcase

always @ ( * )
case ( cd[3:0] )
4'h0 : cd_rm =  r0;
4'h1 : cd_rm =  r1;	
4'h2 : cd_rm =  r2;
4'h3 : cd_rm =  r3;
4'h4 : cd_rm =  r4;
4'h5 : cd_rm =  r5;	
4'h6 : cd_rm =  r6;
4'h7 : cd_rm =  r7;	
4'h8 : cd_rm =  r8;
4'h9 : cd_rm =  r9;	
4'ha : cd_rm =  ra;
4'hb : cd_rm =  rb;
4'hc : cd_rm =  rc;
4'hd : cd_rm =  rd;	
4'he : cd_rm =  re;
4'hf : cd_rm =  rfx;
 endcase	






always @ ( * )
if ( cd_is_msr1|cd_is_dp2 )
   sdvig_hi =  cd[7:0];
else if ( cd_is_ldr0 )
    sdvig_hi =  cd[11:0];
else if ( cd_is_b )
    sdvig_hi =  {{6{cd[23]}},cd[23:0],2'b0};
else if ( cd[4] & cd[7] )
   sdvig_hi =  cd[22] ? {cd[11:8],cd[3:0]} : cd_rm;
else 
    case( cd[6:5] )
	2'h0 : sdvig_hi =  cd_rm;
	2'h1 : sdvig_hi =  32'b0;
	2'h2 : sdvig_hi =  {32{cd_rm[31]}};
	2'h3 : sdvig_hi =  cd_rm;
	endcase

	

	
always @ ( * )
if ( cd_is_msr1|cd_is_dp2 )
    sdvig_lw =  cd[7:0];
else if ( cd[6:5]==2'b0 )
    sdvig_lw =  32'b0;
else 
    sdvig_lw =  cd_rm;

assign rt_nc =  ~cd_rs[4:0] + 1'b1;
assign rt_nb =  ~cd[11:7] + 1'b1;
assign rt_na =  ~cd[11:8] + 1'b1;



	
always @ ( * )
if (cd_is_b|cd_is_ldr0)
    sdvig_rt_n =  5'b0;
else if ( cd_is_msr1|cd_is_dp2 )
    sdvig_rt_n =  {rt_na,1'b0};
else if ( ~cd[4] )
    sdvig_rt_n =  (cd[6:5]==2'b0) ? cd[11:7] : rt_nb;
else if ( cd[7] )
    sdvig_rt_n =  5'b0;
else if ( cd[6:5]==2'b11 )
    sdvig_rt_n =  rt_nc;
else if ( |cd_rs[7:5] )
    sdvig_rt_n =  5'b0;	
else  
    sdvig_rt_n =  (cd[6:5]==2'b0) ? cd_rs[4:0] : rt_nc;



assign sdvig_ot =  {sdvig_hi,sdvig_lw}<<sdvig_rt_n;
	

assign poluchat_rn_num =  (cd_is_b)?4'hf:cd[19:16];	


always @ ( * )
case ( poluchat_rn_num )
4'h0 : poluchat_rn =  r0;
4'h1 : poluchat_rn =  r1;	
4'h2 : poluchat_rn =  r2;
4'h3 : poluchat_rn =  r3;
4'h4 : poluchat_rn =  r4;
4'h5 : poluchat_rn =  r5;	
4'h6 : poluchat_rn =  r6;
4'h7 : poluchat_rn =  r7;	
4'h8 : poluchat_rn =  r8;
4'h9 : poluchat_rn =  r9;	
4'ha : poluchat_rn =  ra;
4'hb : poluchat_rn =  rb;
4'hc : poluchat_rn =  rc;
4'hd : poluchat_rn =  rd;	
4'he : poluchat_rn =  re;
4'hf : poluchat_rn =  rfx;
endcase

assign cd_is_dp =  cd_is_dp0|cd_is_dp1|cd_is_dp2;



always @ ( posedge clk or posedge rst )
if ( rst )
    reg_rn <= #`dil 32'd0;
else if ( cpu_en )
    if ( ~derzhat_en )
	    if ( cd_is_dp & ((cd[24:21]==4'b1101)|(cd[24:21]==4'b1111)) )
		    reg_rn <= #`dil  32'b0;
		else
	        reg_rn <= #`dil  poluchat_rn;
	else if ( command_is_mult|command_is_multl )
	    reg_rn <= #`dil  command[21] ? rt : 32'b0;
	else;
else;

	
assign cd_summa =  (cd[0]+cd[1]+cd[2]+cd[3]+cd[4]+cd[5]+cd[6]+cd[7]+cd[8]+cd[9]+cd[10]+cd[11]+cd[12]+cd[13]+cd[14]+cd[15]);

assign command_is_zagru_m =  (command[27:25]==3'b100);


always @ ( posedge clk or posedge rst )
if ( rst )
    command_summa <= #`dil 5'd0;
else if ( cpu_en & ~derzhat_en )
    command_summa <= #`dil  cd_summa;
else;



	

	
always @ ( posedge clk or posedge rst )
if ( rst )
    sdvig_ans <= #`dil 32'd0;
else if ( cpu_en )
    if ( ~derzhat_en )
        if ( cd_is_zagru_m )
            case( cd[24:23] )
            2'h0 : sdvig_ans <= #`dil  {(cd_summa - 1'b1),2'b0};
            2'h1 : sdvig_ans <= #`dil  0;
            2'h2 : sdvig_ans <= #`dil  {cd_summa,2'b0};
            2'h3 : sdvig_ans <= #`dil  3'b100;
            endcase
        else   
	        sdvig_ans <= #`dil  sdvig_ot[63:32];
	else if ( command_is_zagru_m )
	    if ( summa_m==5'b1 )
	        sdvig_ans[6:2] <= #`dil command_summa;	
	    else if ( command[23] )
	        sdvig_ans[6:2] <= #`dil sdvig_ans[6:2] + 1'b1;
	    else
	        sdvig_ans[6:2] <= #`dil sdvig_ans[6:2] - 1'b1;
	else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    summa_m <= #`dil 5'd0;
else if ( cpu_en )
    if ( ~derzhat_en )
	    if ( cd_is_mult )
	        summa_m <= #`dil  5'b1;
		else if ( cd_is_multl )
            summa_m <= #`dil  5'b10;
        else			
	        summa_m <= #`dil  cd_summa;
	else
	    summa_m <= #`dil  summa_m - 1'b1;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    dp1_lsl_more <= #`dil 1'd0;
else if ( cpu_en )
    if ( ~derzhat_en )
	    dp1_lsl_more <= #`dil  cd_is_dp1 & (cd[6:5]==2'b00) & (|cd_rs[7:5]);
	else
	    dp1_lsl_more <= #`dil  1'b0;
else;


always @ ( posedge clk or posedge rst )
if ( rst )
    dp0_rrx_sdvig <= #`dil 1'd0;
else if ( cpu_en )
    if ( ~derzhat_en )
	    dp0_rrx_sdvig <= #`dil  cd_is_dp0 & (cd[11:5]==7'b00000_11);
	else
	    dp0_rrx_sdvig <= #`dil  1'b0;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    dp1_sdvig_zero <= #`dil 1'b0;
else if ( cpu_en )
    if ( ~derzhat_en )
        dp1_sdvig_zero <= #`dil cd_is_dp1 & (cd_rs[7:0]==8'd0);
    else
	    dp1_sdvig_zero <= #`dil 1'b0;
else;		
	
	
always @ ( * )
if ( command_is_mult|command_is_multl )
    vtoroy_operd =  reg_rs;
else if ( dp1_lsl_more )
    vtoroy_operd =  32'b0;
else if  ( dp1_sdvig_zero )
    vtoroy_operd = sdvig_word;	
else if ( dp0_rrx_sdvig )
    vtoroy_operd =  { cpsr_dc,sdvig_ans[31:1]};
else
    vtoroy_operd =  sdvig_ans;	
	
	


assign add_a =  adder_a_inv ? ~reg_rn : reg_rn;	

always @ ( posedge clk or posedge rst )
if ( rst )
    adder_b_inv <= #`dil 1'd0;
else if ( cpu_en )
    if ( ~derzhat_en )
	    if ( cd_is_b|cd_is_mult )
		    adder_b_inv <= #`dil  1'b0;
		else if ( cd_is_multl )
		    adder_b_inv <= #`dil  cd[22] & ( cd_rm[31] ^ cd_rs[31] );
	    else if ( cd_is_dp )
		    adder_b_inv <= #`dil  ((cd[24:21]==4'b0010)|(cd[24:21]==4'b0110)|(cd[24:21]==4'b1010)|(cd[24:21]==4'b1111)|(cd[24:21]==4'b1110));
		else
		    adder_b_inv <= #`dil  ~cd[23];
	else;
else;	
	
always @ ( posedge clk or posedge rst )
if ( rst )
    adder_a_inv <= #`dil 1'd0;
else if ( cpu_en )
    if ( ~derzhat_en )
	    adder_a_inv <= #`dil  cd_is_dp & ((cd[24:21]==4'b0011)|(cd[24:21]==4'b0111));
	else;
else;	
	
assign add_b =  adder_b_inv ? ~vtoroy_operd : vtoroy_operd;	
	

always @ ( posedge clk or posedge rst )
if ( rst )
    add_extra_num <= #`dil 2'd0;
else if ( cpu_en )
    if ( ~derzhat_en )
		if ( cd_is_b|cd_is_mult )
		    add_extra_num <= #`dil  2'b0;
		else if ( cd_is_multl )
		    add_extra_num <= #`dil  ( cd[22] & ( cd_rm[31]^cd_rs[31] ) ) ? 2'b01 : 2'b00;
	    else if ( cd_is_dp )
            if ( (cd[24:21]==4'b0101)|(cd[24:21]==4'b0110)|(cd[24:21]==4'b0111) )    
                add_extra_num <= #`dil  2'b10;
	        else if ( (cd[24:21]==4'b0010)|(cd[24:21]==4'b0011)|(cd[24:21]==4'b1010) )
	            add_extra_num <= #`dil  2'b1;
	        else
	            add_extra_num <= #`dil  2'b0;
		else
		    add_extra_num <= #`dil  cd[23] ? 2'b0 : 2'b1;
	else;
else;
	
always @ ( * )
if ( command_is_multl & ( summa_m==5'b0 ) )
    add_c =  multl_extra_num;
else if ( add_extra_num[1] )
    add_c =  cpsr_dc;
else
    add_c =  add_extra_num[0];
	
assign summa_sredniy =  add_a[30:0] + add_b[30:0] + add_c;	

assign hi_sredniy =  add_a[31] + add_b[31] + summa_sredniy[31];


assign bit_cy =  hi_sredniy[1];

assign hi_bit =  hi_sredniy[0];


assign bit_ov =  hi_sredniy[1] ^ summa_sredniy[31];	


assign summa_rn_rm =  {hi_bit,summa_sredniy[30:0]};


assign and_ans =  reg_rn & add_b;

assign eor_ans =  reg_rn ^ vtoroy_operd;

assign or_ans =  reg_rn | vtoroy_operd;


always @ ( * )
case ( command[24:21] )
4'h0 : dp_vykhod =  and_ans;
4'h1 : dp_vykhod =  eor_ans;
4'h2 : dp_vykhod =  summa_rn_rm;
4'h3 : dp_vykhod =  summa_rn_rm;
4'h4 : dp_vykhod =  summa_rn_rm;
4'h5 : dp_vykhod =  summa_rn_rm;
4'h6 : dp_vykhod =  summa_rn_rm;
4'h7 : dp_vykhod =  summa_rn_rm;
4'h8 : dp_vykhod =  and_ans;
4'h9 : dp_vykhod =  eor_ans;
4'ha : dp_vykhod =  summa_rn_rm;
4'hb : dp_vykhod =  summa_rn_rm;
4'hc : dp_vykhod =  or_ans;
4'hd : dp_vykhod =  summa_rn_rm;
4'he : dp_vykhod =  and_ans;
4'hf : dp_vykhod =  summa_rn_rm;
endcase


always @ ( posedge clk or posedge rst )
if ( rst )
    cd_to_flag <= #`dil 1'd0;
else if ( cpu_en )
    if ( ~derzhat_en )
	    cd_to_flag <= #`dil  (cd_is_mrs|(cd_is_dp&(cd[24:23]!=2'b10))|((cd_is_ldrh0|cd_is_ldrh1|cd_is_ldrsb0|cd_is_ldrsb1|cd_is_ldrsh0|cd_is_ldrsh1|cd_is_ldr0|cd_is_ldr1)&( cd[21]| ~cd[24])));
	else if ( command_is_mult|command_is_multl )
	    cd_to_flag <= #`dil  1'b1;
	else;
else;


assign to_deystvit =  command_ok & (cd_to_flag|(command_is_zagru_m&command[21]&(summa_m==5'b0)));


always @ ( posedge clk or posedge rst )
if ( rst )
    to_n <= #`dil 4'd0;
else if ( cpu_en )
    if ( ~derzhat_en )
        if ( cd_is_mrs|cd_is_dp )
            to_n <= #`dil  cd[15:12];
        else
            to_n <= #`dil  cd[19:16];
	else if ( command_is_mult|(command_is_multl & (summa_m==5'b1)) )
	    to_n <= #`dil  command[19:16];
	else if ( command_is_multl & ( summa_m==5'b10 ) )
	    to_n <= #`dil  command[15:12];
	else;
else;


always @ ( posedge clk or posedge rst )
if ( rst )
    command_is_mrs <= #`dil 1'd0;
else if ( cpu_en & ~derzhat_en )
    command_is_mrs <= #`dil  cd_is_mrs;
else;


always @ ( posedge clk or posedge rst )
if ( rst )
    command_is_dp <= #`dil 1'd0;
else if ( cpu_en & ~derzhat_en )
    command_is_dp <= #`dil  cd_is_dp;
else;


always @ ( * )
if ( command_is_mrs )
    to_data =  command[22] ? {spsr[10:7],20'b0,spsr[6:5],1'b0,spsr[4:0]} : {cpsr[10:7],20'b0,cpsr[6:5],1'b0,cpsr[4:0]};
else if ( command_is_dp )
    to_data =  dp_vykhod;
else
    to_data =  summa_rn_rm; 	


always @ ( posedge clk or posedge rst )
if ( rst )
    cd_cha_flag <= #`dil 1'd0;
else if ( cpu_en) 
    if ( ~derzhat_en )
        cd_cha_flag <= #`dil  (( cd_is_ldrh0|cd_is_ldrh1|cd_is_ldrsb0|cd_is_ldrsb1|cd_is_ldrsh0|cd_is_ldrsh1|cd_is_ldr0|cd_is_ldr1 ) & cd[20])|cd_is_swp;
    else
	    cd_cha_flag <= #`dil 1'b0;
else;	
	
assign cha_deystvit =  command_ok & cd_cha_flag;	
	
assign cha_num =  command[15:12];	


assign cha_rf_deystvit =  cha_deystvit & ( cha_num==4'hf );	
	

always @ ( posedge clk or posedge rst )
if ( rst )
    cha_fmt <= #`dil 4'd0;
else if ( cpu_en & ~derzhat_en )
    cha_fmt <= #`dil  {(cd_is_ldr0|cd_is_ldr1|cd_is_swp),(cd_is_ldrh0|cd_is_ldrh1),(cd_is_ldrsb0|cd_is_ldrsb1),(cd_is_ldrsh0|cd_is_ldrsh1)};
else;


	
always @ ( posedge clk or posedge rst )
if ( rst )
    go_deystvit <= #`dil 1'd0;
else if ( cpu_en )
    go_deystvit <= #`dil  cha_deystvit;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    go_n <= #`dil 4'd0;
else if ( cpu_en )
    go_n <= #`dil  cha_num;
else;

assign go_rf_deystvit =  go_deystvit & (go_n==4'hf);




	

always @ ( * )
if ( go_fmt[5] )
    go_data =  ram_rdata;
else if ( go_fmt[4] )
    if ( go_fmt[1] )
	    go_data =  {{16{go_fmt[2]&ram_rdata[31]}},ram_rdata[31:16]};
	else
	    go_data =  {{16{go_fmt[2]&ram_rdata[15]}},ram_rdata[15:0]};
else// if ( go_fmt[3] )
    case(go_fmt[1:0])
    2'b00 : go_data =  { {24{go_fmt[2]&ram_rdata[7]}}, ram_rdata[7:0] };
    2'b01 : go_data =  { {24{go_fmt[2]&ram_rdata[15]}}, ram_rdata[15:8] };	
    2'b10 : go_data =  { {24{go_fmt[2]&ram_rdata[23]}}, ram_rdata[23:16] };	
    2'b11 : go_data =  { {24{go_fmt[2]&ram_rdata[31]}}, ram_rdata[31:24] };	
    endcase	

always @ ( posedge clk or posedge rst )
if ( rst )
    go_fmt <= #`dil 6'd0;
else if ( cpu_en )
   if ( cha_fmt[3] )
        go_fmt <= #`dil  command[22] ?{4'b0010,command_addr[1:0]}: {4'b1000,command_addr[1:0]};
    else if ( cha_fmt[2] )
        go_fmt <= #`dil  {4'b0100,command_addr[1:0]};
	else if ( cha_fmt[1] )
	    go_fmt <= #`dil  {4'b0011,command_addr[1:0]};
	else if ( cha_fmt[0] )
        go_fmt <= #`dil  {4'b0101,command_addr[1:0]};
    else
	    go_fmt <= #`dil  {4'b1000,command_addr[1:0]};
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    zagru_m_deystvit <= #`dil 1'd0;
else if ( cpu_en )
    zagru_m_deystvit <= #`dil  command_ok & command_is_zagru_m & command[20] & (summa_m!=5'b0);
else;


always @ ( * )
if ( command[0] )
    zagru_m_vybirat =  4'h0;
else if ( command[1] )
    zagru_m_vybirat =  4'h1; 
else if ( command[2] )
    zagru_m_vybirat =  4'h2; 
else if ( command[3] )
    zagru_m_vybirat =  4'h3; 
else if ( command[4] )
    zagru_m_vybirat =  4'h4; 
else if ( command[5] )
    zagru_m_vybirat =  4'h5; 
else if ( command[6] )
    zagru_m_vybirat =  4'h6; 
else if ( command[7] )
    zagru_m_vybirat =  4'h7; 
else if ( command[8] )
    zagru_m_vybirat =  4'h8; 
else if ( command[9] )
    zagru_m_vybirat =  4'h9; 
else if ( command[10] )
    zagru_m_vybirat =  4'ha; 
else if ( command[11] )
    zagru_m_vybirat =  4'hb; 
else if ( command[12] )
    zagru_m_vybirat =  4'hc; 
else if ( command[13] )
    zagru_m_vybirat =  4'hd; 
else if ( command[14] )
    zagru_m_vybirat =  4'he; 
else if ( command[15] )
    zagru_m_vybirat =  4'hf; 
else 
    zagru_m_vybirat =  4'h0;
	

always @ ( posedge clk or posedge rst )
if ( rst )
    zagru_m_num <= #`dil 4'd0;
else if ( cpu_en )
    zagru_m_num <= #`dil  zagru_m_vybirat;
else;

assign zagru_m_data =  go_data;	
assign zagru_m_rf_deystvit =  (zagru_m_deystvit & ( zagru_m_num==4'hf )) ;
assign zagru_m_usr =  command[20] &  command[22] & ~command[15];

always @ ( posedge clk or posedge rst )
if ( rst )
    cd_cen <= #`dil 1'd0;
else if ( cpu_en & ~derzhat_en )
    cd_cen <= #`dil  (cd_is_ldrh0|cd_is_ldrh1|cd_is_ldrsb0|cd_is_ldrsb1|cd_is_ldrsh0|cd_is_ldrsh1|cd_is_ldr0|cd_is_ldr1|cd_is_swp);
else;


assign ram_cen =  cpu_en & command_ok & (cd_cen|(command_is_zagru_m &(summa_m!=5'b0)));


assign ram_wen =  command_is_swp ? 1'b0 : ~command[20];	


always @ ( posedge clk or posedge rst )
if ( rst )
    command_is_swp <= #`dil 1'd0;
else if ( cpu_en )
    if ( ~derzhat_en )
	    command_is_swp <= #`dil  cd_is_swp;
	else
	    command_is_swp <= #`dil  1'b0;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    command_is_swpx <= #`dil 1'd0;
else if ( cpu_en )
    command_is_swpx <= #`dil  command_is_swp;
else;


always @ ( * )
if ( cha_fmt[3] )
    ram_flag =  command[22]? (1'b1<<command_addr[1:0]):4'b1111;
else if ( cha_fmt[2]|cha_fmt[0] )
    ram_flag =  command_addr[1] ? 4'b1100 : 4'b0011;
else if ( cha_fmt[1] ) 
    ram_flag =  1'b1<<command_addr[1:0];
else
    ram_flag =  4'b1111;	


assign command_addr =  ( (command[24]|command_is_zagru_m)& ~command_is_swp & ~command_is_swpx ) ? summa_rn_rm : reg_rn;	
	

assign ram_addr =  {command_addr[31:2],2'b0};	
	
	
always @ ( posedge clk or posedge rst )
if ( rst )
    cd_rt_num <= #`dil 4'd0;
else if ( cpu_en )
    if ( ~derzhat_en )
	    cd_rt_num <= #`dil  cd_is_swp ? cd[3:0] : cd[15:12];
    else if ( command_is_multl )
	    cd_rt_num <= #`dil  command[19:16];
	else;
else;
	
	
assign rt_num =  command_is_zagru_m ? zagru_m_vybirat : cd_rt_num;	
		
always @ ( * )
case ( rt_num )
4'h0 : rt =  r0;
4'h1 : rt =  r1;	
4'h2 : rt =  r2;
4'h3 : rt =  r3;
4'h4 : rt =  r4;
4'h5 : rt =  r5;	
4'h6 : rt =  r6;
4'h7 : rt =  r7;	
4'h8 : rt =  r8;
4'h9 : rt =  r9;	
4'ha : rt =  ra;
4'hb : rt =  rb;
4'hc : rt =  rc;
4'hd : rt =  rd;	
4'he : rt =  re;
4'hf : rt =  rf;
endcase


always @ ( * )
if ( cha_fmt[3] )
    if ( command[22] )
	    ram_wdata =  { rt[7:0],rt[7:0],rt[7:0],rt[7:0]};
    else
        ram_wdata =  rt;	
else if ( cha_fmt[2] )
    ram_wdata =  {rt[15:0],rt[15:0]};
else
    ram_wdata =  rt;
	

always @ ( posedge clk or posedge rst )
if ( rst )
    r0 <= #`dil 32'd0;
else if ( cpu_en )
    if ( zagru_m_deystvit & ( zagru_m_num == 4'h0 ) )
	    r0 <= #`dil  zagru_m_data;
	else if ( go_deystvit & ( go_n == 4'h0 ) )
	    r0 <= #`dil  go_data;
	else if ( to_deystvit & ( to_n == 4'h0 ) )
	    r0 <= #`dil  to_data;
	else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    r1 <= #`dil 32'd0;
else if ( cpu_en )
    if ( zagru_m_deystvit & ( zagru_m_num == 4'h1 ) )
	    r1 <= #`dil  zagru_m_data;
	else if ( go_deystvit & ( go_n == 4'h1 ) )
	    r1 <= #`dil  go_data;
	else if ( to_deystvit & ( to_n == 4'h1 ) )
	    r1 <= #`dil  to_data;
	else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    r2 <= #`dil 32'd0;
else if ( cpu_en )
    if ( zagru_m_deystvit & ( zagru_m_num == 4'h2 ) )
	    r2 <= #`dil  zagru_m_data;
	else if ( go_deystvit & ( go_n == 4'h2 ) )
	    r2 <= #`dil  go_data;
	else if ( to_deystvit & ( to_n == 4'h2 ) )
	    r2 <= #`dil  to_data;
	else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    r3 <= #`dil 32'd0;
else if ( cpu_en )
    if ( zagru_m_deystvit & ( zagru_m_num==4'h3 ) )
	    r3 <= #`dil  zagru_m_data;
	else if ( go_deystvit & ( go_n == 4'h3 ) )
	    r3 <= #`dil  go_data;
	else if ( to_deystvit & ( to_n == 4'h3 ) )
	    r3 <= #`dil  to_data;
	else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    r4 <= #`dil 32'd0;
else if ( cpu_en )
    if ( zagru_m_deystvit & ( zagru_m_num == 4'h4 ) )
	    r4 <= #`dil  zagru_m_data;
	else if ( go_deystvit & ( go_n == 4'h4 ) )
	    r4 <= #`dil  go_data;
	else if ( to_deystvit & ( to_n == 4'h4 ) )
	    r4 <= #`dil  to_data;
	else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    r5 <= #`dil 32'd0;
else if ( cpu_en )
    if ( zagru_m_deystvit & ( zagru_m_num == 4'h5 ) )
	    r5 <= #`dil  zagru_m_data;
	else if ( go_deystvit & ( go_n == 4'h5 ) )
	    r5 <= #`dil  go_data;
	else if ( to_deystvit & ( to_n == 4'h5 ) )
	    r5 <= #`dil  to_data;
	else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    r6 <= #`dil 32'd0;
else if ( cpu_en )
    if ( zagru_m_deystvit & ( zagru_m_num == 4'h6 ) )
	    r6 <= #`dil  zagru_m_data;
	else if ( go_deystvit & ( go_n == 4'h6 ) )
	    r6 <= #`dil  go_data;
	else if ( to_deystvit & ( to_n == 4'h6 ) )
	    r6 <= #`dil  to_data;
	else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    r7 <= #`dil 32'd0;
else if ( cpu_en )
    if ( zagru_m_deystvit & ( zagru_m_num == 4'h7 ) )
	    r7 <= #`dil  zagru_m_data;
	else if ( go_deystvit & ( go_n == 4'h7 ) )
	    r7 <= #`dil  go_data;
	else if ( to_deystvit & ( to_n == 4'h7 ) )
	    r7 <= #`dil  to_data;
	else;
else;



always @ ( posedge clk or posedge rst )
if ( rst )
    r8 <= #`dil 32'd0;
else if ( cpu_en )
    if ( cpsr_dm!=m_after )
	    r8 <= #`dil  (cpsr_dm == 5'b10001) ? r8_fiq : r8_usr;
	else if ( zagru_m_deystvit & ( zagru_m_num==4'h8 ) & ~( zagru_m_usr & ( cpsr_dm==5'b10001 ) ) )
	    r8 <= #`dil  zagru_m_data;		
	else if ( go_deystvit & ( go_n==4'h8 ) )
	    r8 <= #`dil  go_data;
	else if ( to_deystvit & ( to_n==4'h8 ) )
	    r8 <= #`dil  to_data;
	else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    r8_fiq <= #`dil 32'd0;
else if ( cpu_en )
    if ( zagru_m_deystvit & ( zagru_m_num==4'h8 )& ( ~zagru_m_usr & (cpsr_dm==5'b10001 ) ) )
	    r8_fiq <= #`dil  zagru_m_data;
	else if ( go_deystvit & (go_n==4'h8 ) & (cpsr_dm==5'b10001 ) )
	    r8_fiq <= #`dil  go_data;
	else if ( to_deystvit  & ( to_n== 4'h8 ) & (cpsr_dm==5'b10001 )  )
	    r8_fiq <= #`dil  to_data;
	else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    r8_usr <= #`dil 32'd0;
else if ( cpu_en )
    if ( zagru_m_deystvit & ( zagru_m_num==4'h8 ) & ( zagru_m_usr | (cpsr_dm!=5'b10001 ) ) )
	    r8_usr <= #`dil  zagru_m_data;
	else if ( go_deystvit & (go_n==4'h8 ) & (cpsr_dm!=5'b10001 ) )
	    r8_usr <= #`dil  go_data;
	else if ( to_deystvit & ( to_n== 4'h8 ) & (cpsr_dm!=5'b10001 )  )
        r8_usr <= #`dil  to_data;
	else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    r9 <= #`dil 32'd0;
else if ( cpu_en )
    if ( cpsr_dm!=m_after )
	    r9 <= #`dil  (cpsr_dm==5'b10001) ? r9_fiq : r9_usr;
	else if ( zagru_m_deystvit & ( zagru_m_num==4'h9 ) & ~( zagru_m_usr & ( cpsr_dm==5'b10001 ) ) )
	    r9 <= #`dil  zagru_m_data;
	else if ( go_deystvit & (go_n==4'h9) )
	    r9 <= #`dil  go_data;
	else if ( to_deystvit & (to_n==4'h9) )
	    r9 <= #`dil  to_data;
	else;
else; 

always @ ( posedge clk or posedge rst )
if ( rst )
    r9_fiq <= #`dil 32'd0;
else if ( cpu_en )
    if ( zagru_m_deystvit & ( zagru_m_num==4'h9 )& ( ~zagru_m_usr & (cpsr_dm==5'b10001 ) ) )
	    r9_fiq <= #`dil  zagru_m_data;
	else if ( go_deystvit & (go_n==4'h9 ) & (cpsr_dm==5'b10001 ) )
	    r9_fiq <= #`dil  go_data;
	else if ( to_deystvit  & ( to_n== 4'h9 ) & (cpsr_dm==5'b10001 )  )
	    r9_fiq <= #`dil  to_data;
	else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    r9_usr <= #`dil 32'd0;
else if ( cpu_en )
    if ( zagru_m_deystvit & ( zagru_m_num==4'h9 ) & ( zagru_m_usr | (cpsr_dm!=5'b10001 ) ) )
	    r9_usr <= #`dil  zagru_m_data;
	else if ( go_deystvit & (go_n==4'h9 ) & (cpsr_dm!=5'b10001 ) )
	    r9_usr <= #`dil  go_data;
	else if ( to_deystvit  & ( to_n== 4'h9 ) & (cpsr_dm!=5'b10001 )  )
	    r9_usr <= #`dil  to_data;
	else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    ra <= #`dil 32'd0;
else if ( cpu_en )
    if ( cpsr_dm!=m_after )
	    ra <= #`dil  ( cpsr_dm == 5'b10001 ) ? ra_fiq : ra_usr;
	else if ( zagru_m_deystvit & ( zagru_m_num==4'ha ) & ~( zagru_m_usr & ( cpsr_dm==5'b10001 ) ) )
	    ra <= #`dil  zagru_m_data;
	else if ( go_deystvit & (go_n==4'ha) )
	    ra <= #`dil  go_data;
	else if ( to_deystvit & (to_n==4'ha) )
	    ra <= #`dil  to_data;
	else;
else; 

always @ ( posedge clk or posedge rst )
if ( rst )
    ra_fiq <= #`dil 32'd0;
else if ( cpu_en )
    if ( zagru_m_deystvit & ( zagru_m_num==4'ha )& ( ~zagru_m_usr & (cpsr_dm==5'b10001 ) ) )
	    ra_fiq <= #`dil  zagru_m_data;
	else if ( go_deystvit & (go_n==4'ha ) & (cpsr_dm==5'b10001 ) )
	    ra_fiq <= #`dil  go_data;
	else if ( to_deystvit  & ( to_n== 4'ha ) & (cpsr_dm==5'b10001 )  )
	    ra_fiq <= #`dil  to_data;
	else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    ra_usr <= #`dil 32'd0;
else if ( cpu_en )
    if ( zagru_m_deystvit & ( zagru_m_num==4'ha ) & ( zagru_m_usr | (cpsr_dm!=5'b10001 ) ) )
	    ra_usr <= #`dil  zagru_m_data;
	else if ( go_deystvit & (go_n==4'ha ) & (cpsr_dm!=5'b10001 ) )
	    ra_usr <= #`dil  go_data;
	else if ( to_deystvit  & ( to_n== 4'ha ) & (cpsr_dm!=5'b10001 )  )
	    ra_usr <= #`dil  to_data;
	else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    rb <= #`dil 32'd0;
else if ( cpu_en )
    if ( cpsr_dm!=m_after )
	    rb <= #`dil  ( cpsr_dm == 5'b10001 ) ? rb_fiq : rb_usr;
	else if ( zagru_m_deystvit & ( zagru_m_num==4'hb ) & ~( zagru_m_usr & ( cpsr_dm==5'b10001 ) ) )
	    rb <= #`dil  zagru_m_data;
	else if ( go_deystvit & (go_n==4'hb) )
	    rb <= #`dil  go_data;
	else if ( to_deystvit & (to_n==4'hb) )
	    rb <= #`dil  to_data;
	else;
else;  

always @ ( posedge clk or posedge rst )
if ( rst )
    rb_fiq <= #`dil 32'd0;
else if ( cpu_en )
    if ( zagru_m_deystvit & ( zagru_m_num==4'hb )& ( ~zagru_m_usr & (cpsr_dm==5'b10001 ) ) )
	    rb_fiq <= #`dil  zagru_m_data;
	else if ( go_deystvit & (go_n==4'hb ) & (cpsr_dm==5'b10001 ) )
	    rb_fiq <= #`dil  go_data;
	else if ( to_deystvit  & ( to_n== 4'hb ) & (cpsr_dm==5'b10001 )  )
	    rb_fiq <= #`dil  to_data;
	else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    rb_usr <= #`dil 32'd0;
else if ( cpu_en )
    if ( zagru_m_deystvit & ( zagru_m_num==4'hb ) & ( zagru_m_usr | (cpsr_dm!=5'b10001 ) ) )
	    rb_usr <= #`dil  zagru_m_data;
	else if ( go_deystvit & (go_n==4'hb ) & (cpsr_dm!=5'b10001 ) )
	    rb_usr <= #`dil  go_data;
	else if ( to_deystvit  & ( to_n== 4'hb ) & (cpsr_dm!=5'b10001 )  )
	    rb_usr <= #`dil  to_data;
	else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    rc <= #`dil 32'd0;
else if ( cpu_en )
    if ( cpsr_dm!=m_after )
	    rc <= #`dil  ( cpsr_dm == 5'b10001 ) ? rc_fiq : rc_usr;
	else if ( zagru_m_deystvit & ( zagru_m_num==4'hc ) & ~( zagru_m_usr & ( cpsr_dm==5'b10001 ) ) )
	    rc <= #`dil  zagru_m_data;
	else if ( go_deystvit & (go_n==4'hc) )
	    rc <= #`dil  go_data;
	else if ( to_deystvit & (to_n==4'hc) )
	    rc <= #`dil  to_data;
	else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    rc_fiq <= #`dil 32'd0;
else if ( cpu_en )
    if ( zagru_m_deystvit & ( zagru_m_num==4'hc )& ( ~zagru_m_usr & (cpsr_dm==5'b10001 ) ) )
	    rc_fiq <= #`dil  zagru_m_data;
	else if ( go_deystvit & (go_n==4'hc ) & (cpsr_dm==5'b10001 ) )
	    rc_fiq <= #`dil  go_data;
	else if ( to_deystvit  & ( to_n== 4'hc ) & (cpsr_dm==5'b10001 )  )
	    rc_fiq <= #`dil  to_data;
	else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    rc_usr <= #`dil 32'd0;
else if ( cpu_en )
    if ( zagru_m_deystvit & ( zagru_m_num==4'hc ) & ( zagru_m_usr | (cpsr_dm!=5'b10001 ) ) )
	    rc_usr <= #`dil  zagru_m_data;
	else if ( go_deystvit & (go_n==4'hc ) & (cpsr_dm!=5'b10001 ) )
	    rc_usr <= #`dil  go_data;
	else if ( to_deystvit  & ( to_n== 4'hc ) & (cpsr_dm!=5'b10001 )  )
	    rc_usr <= #`dil  to_data;
	else;
else;




always @ ( posedge clk or posedge rst )
if ( rst )
    rd <= #`dil 32'd0;
else if ( cpu_en )
    if ( cpsr_dm!=m_after )
        case ( cpsr_dm )
        5'b10001 : rd <= #`dil  rd_fiq;
        5'b11011 : rd <= #`dil  rd_und;
        5'b10010 : rd <= #`dil  rd_irq;
        5'b10111 : rd <= #`dil  rd_abt;  
        5'b10011 : rd <= #`dil  rd_svc;
        default  : rd <= #`dil  rd_usr;
        endcase	
	else if ( zagru_m_deystvit & (zagru_m_num==4'hd) & ~( zagru_m_usr & ((cpsr_dm==5'b10001)|(cpsr_dm==5'b11011)|(cpsr_dm==5'b10010)|(cpsr_dm==5'b10111)|(cpsr_dm==5'b10011)) ) )
	    rd <= #`dil  zagru_m_data;
	else if ( go_deystvit & ( go_n==4'hd ) )
	    rd <= #`dil  go_data;
	else if ( to_deystvit & ( to_n==4'hd ) )
	    rd <= #`dil  to_data;
	else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    rd_abt <= #`dil 32'd0;
else if ( cpu_en )
    if ( zagru_m_deystvit & ( zagru_m_num==4'hd )& ( ~zagru_m_usr & (cpsr_dm==5'b10111 ) ) )
	    rd_abt <= #`dil  zagru_m_data;
	else if ( go_deystvit & (go_n==4'hd ) & (cpsr_dm==5'b10111 ) )
	    rd_abt <= #`dil  go_data;
	else if ( to_deystvit  & ( to_n== 4'hd ) & (cpsr_dm==5'b10111 )  )
	    rd_abt <= #`dil  to_data;
	else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    rd_fiq <= #`dil 32'd0;
else if ( cpu_en )
    if ( zagru_m_deystvit & ( zagru_m_num==4'hd )& ( ~zagru_m_usr & (cpsr_dm==5'b10001 ) ) )
	    rd_fiq <= #`dil  zagru_m_data;
	else if ( go_deystvit & (go_n==4'hd ) & (cpsr_dm==5'b10001 ) )
	    rd_fiq <= #`dil  go_data;
	else if ( to_deystvit  & ( to_n== 4'hd ) & (cpsr_dm==5'b10001 )  )
	    rd_fiq <= #`dil  to_data;
	else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    rd_irq <= #`dil 32'd0;
else if ( cpu_en )
    if ( zagru_m_deystvit & ( zagru_m_num==4'hd )& ( ~zagru_m_usr & (cpsr_dm==5'b10010 ) ) )
	    rd_irq <= #`dil  zagru_m_data;
	else if ( go_deystvit & (go_n==4'hd ) & (cpsr_dm==5'b10010 ) )
	    rd_irq <= #`dil  go_data;
	else if ( to_deystvit  & ( to_n== 4'hd ) & (cpsr_dm==5'b10010 )  )
	    rd_irq <= #`dil  to_data;
	else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    rd_svc <= #`dil 32'd0;
else if ( cpu_en )
    if ( zagru_m_deystvit & ( zagru_m_num==4'hd )& ( ~zagru_m_usr & (cpsr_dm==5'b10011 ) ) )
	    rd_svc <= #`dil  zagru_m_data;
	else if ( go_deystvit & (go_n==4'hd ) & (cpsr_dm==5'b10011 ) )
	    rd_svc <= #`dil  go_data;
	else if ( to_deystvit  & ( to_n== 4'hd ) & (cpsr_dm==5'b10011 )  )
	    rd_svc <= #`dil  to_data;
	else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    rd_und <= #`dil 32'd0;
else if ( cpu_en )
    if ( zagru_m_deystvit & ( zagru_m_num==4'hd )& ( ~zagru_m_usr & (cpsr_dm==5'b11011 ) ) )
	    rd_und <= #`dil  zagru_m_data;
	else if ( go_deystvit & (go_n==4'hd ) & (cpsr_dm==5'b11011 ) )
	    rd_und <= #`dil  go_data;
	else if ( to_deystvit  & ( to_n== 4'hd ) & (cpsr_dm==5'b11011 )  )
	    rd_und <= #`dil  to_data;
	else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    rd_usr <= #`dil 32'd0;
else if ( cpu_en )
    if ( zagru_m_deystvit & ( zagru_m_num==4'hd ) & ( zagru_m_usr | ((cpsr_dm!=5'b10001)&(cpsr_dm!=5'b11011)&(cpsr_dm!=5'b10010)&(cpsr_dm!=5'b10111)&(cpsr_dm!=5'b10011)) ) )
	    rd_usr <= #`dil  zagru_m_data;
	else if ( go_deystvit & (go_n==4'hd ) & ((cpsr_dm!=5'b10001)&(cpsr_dm!=5'b11011)&(cpsr_dm!=5'b10010)&(cpsr_dm!=5'b10111)&(cpsr_dm!=5'b10011)) )
	    rd_usr <= #`dil  go_data;
	else if ( to_deystvit  & ( to_n== 4'hd ) & ((cpsr_dm!=5'b10001)&(cpsr_dm!=5'b11011)&(cpsr_dm!=5'b10010)&(cpsr_dm!=5'b10111)&(cpsr_dm!=5'b10011)) )
	    rd_usr <= #`dil  to_data;
	else;
else;


always @ ( posedge clk or posedge rst )
if ( rst )
    re <= #`dil 32'd0;
else if ( cpu_en )
    if ( cpsr_dm!=m_after )_
        case ( cpsr_dm )
        5'b10001 : re <= #`dil  re_fiq;
        5'b11011 : re <= #`dil  re_und;
        5'b10010 : re <= #`dil  re_irq;
        5'b10111 : re <= #`dil  re_abt;  
        5'b10011 : re <= #`dil  re_svc;
        default  : re <= #`dil  re_usr;
        endcase	
	else if ( zagru_m_deystvit & (zagru_m_num==4'he) & ~( zagru_m_usr & ((cpsr_dm==5'b10001)|(cpsr_dm==5'b11011)|(cpsr_dm==5'b10010)|(cpsr_dm==5'b10111)|(cpsr_dm==5'b10011)) ) )
	    re <= #`dil  zagru_m_data;
	else if ( go_deystvit & ( go_n==4'he ) )
	    re <= #`dil  go_data;
	else if ( command_ok & command_is_b & command[24] )
	    re <= #`dil  rf_b;
	else if ( to_deystvit & ( to_n==4'he ) )
	    re <= #`dil  to_data;
	else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    re_abt <= #`dil 32'd0;
else if ( cpu_en )
    if ( ram_abort | ( ~fiq_en & ~irq_en & ( command_flag & cd_abort ) ) )
        re_abt <= #`dil  rf_b;		
    else if ( zagru_m_deystvit & ( zagru_m_num==4'he ) & ( ~zagru_m_usr & (cpsr_dm==5'b10111) ) )
	    re_abt <= #`dil  zagru_m_data;
	else if ( go_deystvit & (go_n==4'he ) & (cpsr_dm==5'b10111) )
	    re_abt <= #`dil  go_data;
	else if ( command_ok & command_is_b & command[24] & (cpsr_dm==5'b10111) )
	    re_abt <= #`dil  rf_b;
	else if ( to_deystvit  & ( to_n== 4'he ) & (cpsr_dm==5'b10111) )
	    re_abt <= #`dil  to_data;
	else;
else;		

always @ ( posedge clk or posedge rst )
if ( rst )
    re_fiq <= #`dil 32'd0;
else if ( cpu_en )
    if ( fiq_en )
	    if ( ram_abort )
		    re_fiq <= #`dil  32'h10;
        else
		    re_fiq <= #`dil  rf_b;
    else if ( zagru_m_deystvit & ( zagru_m_num==4'he ) & ( ~zagru_m_usr & (cpsr_dm==5'b10001) ) )
	    re_fiq <= #`dil  zagru_m_data;
	else if ( go_deystvit & (go_n==4'he ) & (cpsr_dm==5'b10001) )
	    re_fiq <= #`dil  go_data;
	else if ( command_ok & command_is_b & command[24] & (cpsr_dm==5'b10001) )
	    re_fiq <= #`dil  rf_b;
	else if ( to_deystvit  & ( to_n== 4'he ) & (cpsr_dm==5'b10001) )
	    re_fiq <= #`dil  to_data;
	else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    re_irq <= #`dil 32'd0;
else if ( cpu_en )
    if  ( ~ram_abort & ~fiq_en & irq_en )
        re_irq <= #`dil  rf_b;	
    else if ( zagru_m_deystvit & ( zagru_m_num==4'he ) & ( ~zagru_m_usr & (cpsr_dm==5'b10010) ) )
	    re_irq <= #`dil  zagru_m_data;
	else if ( go_deystvit & (go_n==4'he ) & (cpsr_dm==5'b10010) )
	    re_irq <= #`dil  go_data;
	else if ( command_ok & command_is_b & command[24] & (cpsr_dm==5'b10010) )
	    re_irq <= #`dil  rf_b;
	else if ( to_deystvit  & ( to_n== 4'he ) & (cpsr_dm==5'b10010) )
	    re_irq <= #`dil  to_data;
	else;
else;		

always @ ( posedge clk or posedge rst )
if ( rst )
    re_svc <= #`dil 32'd0;
else if ( cpu_en )
    if ( ~ram_abort & ~fiq_en & ~irq_en & ( command_flag & ~cd_abort & ~cd_und & (cond_satisfy & command_is_swi) ) )
        re_svc <= #`dil  rf_b;
    else if ( zagru_m_deystvit & ( zagru_m_num==4'he ) & ( ~zagru_m_usr & (cpsr_dm==5'b10011) ) )
	    re_svc <= #`dil  zagru_m_data;
	else if ( go_deystvit & (go_n==4'he ) & (cpsr_dm==5'b10011) )
	    re_svc <= #`dil  go_data;
	else if ( command_ok & command_is_b & command[24] & (cpsr_dm==5'b10011) )
	    re_svc <= #`dil  rf_b;
	else if ( to_deystvit  & ( to_n== 4'he ) & (cpsr_dm==5'b10011) )
	    re_svc <= #`dil  to_data;
	else;
else;		

always @ ( posedge clk or posedge rst )
if ( rst )
    re_und <= #`dil 32'd0;
else if ( cpu_en )
    if ( ~ram_abort & ~fiq_en & ~irq_en & ( command_flag & ~cd_abort & cd_und ) )
	    re_und <= #`dil  rf_b;
    else if ( zagru_m_deystvit & ( zagru_m_num==4'he ) & ( ~zagru_m_usr & (cpsr_dm==5'b11011) ) )
	    re_und <= #`dil  zagru_m_data;
	else if ( go_deystvit & (go_n==4'he ) & (cpsr_dm==5'b11011) )
	    re_und <= #`dil  go_data;
	else if ( command_ok & command_is_b & command[24] & (cpsr_dm==5'b11011) )
	    re_und <= #`dil  rf_b;
	else if ( to_deystvit  & ( to_n== 4'he ) & (cpsr_dm==5'b11011) )
	    re_und <= #`dil  to_data;
	else;
else;		

always @ ( posedge clk or posedge rst )
if ( rst )
    re_usr <= #`dil 32'd0;
else if ( cpu_en )
    if ( zagru_m_deystvit & ( zagru_m_num==4'he ) & ( zagru_m_usr | 
	 ((cpsr_dm!=5'b10001)&(cpsr_dm!=5'b11011)&(cpsr_dm!=5'b10010)&(cpsr_dm!=5'b10111)&(cpsr_dm!=5'b10011)) ) )
	    re_usr <= #`dil  zagru_m_data;
	else if ( go_deystvit & (go_n==4'he ) & ((cpsr_dm!=5'b10001)&(cpsr_dm!=5'b11011)
			&(cpsr_dm!=5'b10010)&(cpsr_dm!=5'b10111)&(cpsr_dm!=5'b10011)) )
	    re_usr <= #`dil  go_data;
	else if ( command_ok & command_is_b & command[24] & ((cpsr_dm!=5'b10001)&(cpsr_dm!=5'b11011)&(cpsr_dm!=5'b10010)&(cpsr_dm!=5'b10111)&(cpsr_dm!=5'b10011)) )
	    re_usr <= #`dil  rf_b;
	else if ( to_deystvit  & ( to_n== 4'he ) & ((cpsr_dm!=5'b10001)&(cpsr_dm!=5'b11011)&(cpsr_dm!=5'b10010)&(cpsr_dm!=5'b10111)&(cpsr_dm!=5'b10011)) )
	    re_usr <= #`dil  to_data;
	else;
else;


always @ ( posedge clk or posedge rst )
if ( rst )
    zagru_m_change <= #`dil 1'd0;
else if ( cpu_en )
    if ( ~derzhat_en )
	    zagru_m_change <= #`dil  cd[22] & cd[20] & cd[15];
	else;
else;


always @ ( posedge clk or posedge rst )
if ( rst )
    command_is_msr <= #`dil 1'd0;
else if ( cpu_en & ~derzhat_en )
    command_is_msr <= #`dil  cd_is_msr0|cd_is_msr1;
else;


always @ ( * )
if ( command_ok & command_is_dp & command[20] )
    cpsr_dn_in =  ( command[15:12]==4'hf ) ? spsr[10] : dp_vykhod[31];
else if ( command_ok & command_is_zagru_m & zagru_m_change & (summa_m==5'b0) )
    cpsr_dn_in =  spsr[10];
else if ( command_ok & command_is_msr & ~command[22] & command[19] )
    cpsr_dn_in =  vtoroy_operd[31];
else if ( command_ok & (command_is_mult|command_is_multl) & command[20] & (summa_m==5'b0) )
    cpsr_dn_in =  summa_rn_rm[31];
else
    cpsr_dn_in =  cpsr_dn;
	
always @ ( posedge clk or posedge rst )
if ( rst )
    cpsr_dn <= #`dil 1'd0;
else if ( cpu_en )
    cpsr_dn <= #`dil  cpsr_dn_in;
else;	
	

always @ ( posedge clk or posedge rst )
if ( rst )
    multl_z <= #`dil 1'b0;
else if (cpu_en)
    if ( command_is_multl & (summa_m==5'b1) )
	    multl_z <= #`dil  ( summa_rn_rm==32'b0 );
	else;
else;


always @ ( * )
if ( command_ok & command_is_dp & command[20] )
    cpsr_dz_in =  ( command[15:12]==4'hf ) ? spsr[9] : (dp_vykhod==32'b0);	
else if ( command_ok & command_is_zagru_m & zagru_m_change & (summa_m==5'b0) )
    cpsr_dz_in =  spsr[9];
else if ( command_ok & command_is_msr & ~command[22] & command[19] )
    cpsr_dz_in =  vtoroy_operd[30];
else if ( command_ok & command[20] & command_is_mult & (summa_m==5'b0) )
    cpsr_dz_in =  ( summa_rn_rm==32'b0 );
else if ( command_ok & command[20] & command_is_multl & (summa_m==5'b0) )
    cpsr_dz_in =  multl_z & ( summa_rn_rm==32'b0 );	
else
    cpsr_dz_in =  cpsr_dz;
	
always @ ( posedge clk or posedge rst )
if ( rst )
    cpsr_dz <= #`dil 1'd0;
else if ( cpu_en )
    cpsr_dz <= #`dil  cpsr_dz_in;
else;


always @ ( * )
if ( command_ok & command_is_dp & command[20] )
    if ( command[15:12]==4'hf )
        cpsr_dc_in =  spsr[8];
    else if ( (command[24:21]==4'b1011)|(command[24:21]==4'b0100)|(command[24:21]==4'b0101)|
	 (command[24:21]==4'b0011)|(command[24:21]==4'b0111)|(command[24:21]==4'b1010)|
	 (command[24:21]==4'b0010)|(command[24:21]==4'b0110) )
	    cpsr_dc_in =  bit_cy;	
    else
        cpsr_dc_in =  sdvig_bit;
else if ( command_ok & command_is_zagru_m & zagru_m_change & (summa_m==5'b0) )
    cpsr_dc_in =  spsr[8];
else if ( command_ok & command_is_msr & ~command[22] & command[19] )
    cpsr_dc_in =  vtoroy_operd[29];
else
    cpsr_dc_in =  cpsr_dc;

always @ ( posedge clk or posedge rst )
if ( rst )
    cpsr_dc <= #`dil 1'd0;
else if ( cpu_en )
    cpsr_dc <= #`dil  cpsr_dc_in;
else;


always @ ( posedge clk or posedge rst )
if ( rst )
    sdvig_word <= #`dil 32'd0;
else if ( cpu_en )
    if ( ~derzhat_en )
	    if ( cd[27:25]==3'b001 )
		    sdvig_word <= #`dil  cd[7:0];
		else if ( cd_is_multl & cd[22] & cd_rm[31] )
		    sdvig_word <= #`dil  ~cd_rm + 1'b1;
		else 
            sdvig_word <= #`dil  cd_rm;
	else if ( command_is_multl & ( summa_m==5'b10 ) ) 
	    sdvig_word <= #`dil  mult_ans[63:32];
    else;
else;		

assign rot_numd =  cd[11:7] - 1'b1;

assign rot_nume =  cd_rs[4:0] - 1'b1;
	

always @ ( posedge clk or posedge rst )
if ( rst )
    sdvig_num <= #`dil 7'd0;
else if ( cpu_en )
    if ( ~derzhat_en )
	    if ( cd_is_dp2 )
		    sdvig_num <= #`dil  (cd[11:8]==4'h0) ? 7'b10_00000 : {2'b0,rt_na,1'b0};
		else if ( cd_is_dp0 )
		    case( cd[6:5] )
			2'h0 : sdvig_num <= #`dil  (cd[11:7]==5'b0) ? 7'b10_00000 : rt_nb;
			2'h1 : sdvig_num <= #`dil   rot_numd;
			2'h2 : sdvig_num <= #`dil   rot_numd;
			2'h3 : sdvig_num <= #`dil  (cd[11:7]==5'b0) ? 7'b0 : rot_numd;
			endcase
		else //if ( cd_is_dp1 )
		    if ( cd_rs[7:0] == 8'b0 )
			    sdvig_num <= #`dil  7'b10_00000;
			else
   			    case( cd[6:5] )
			    2'h0 : sdvig_num <= #`dil  ( cd_rs[7:0]>8'd32 ) ? 7'b01_00000 : rt_nc;
				2'h1 : sdvig_num <= #`dil  ( cd_rs[7:0]>8'd32 ) ? 7'b01_00000 : rot_nume;
                2'h2 : sdvig_num <= #`dil  ( cd_rs[7:0]>8'd32 ) ? 7'b00_11111 : rot_nume;	
                2'h3 : sdvig_num <= #`dil  ( cd_rs[7:0]==8'd32 )? 7'b10_00000 : rot_nume;
                endcase				
	else;
else;	
	
always @ ( * )
if ( sdvig_num[6] )
    sdvig_bit =  cpsr_dc;
else if ( sdvig_num[5] )
    sdvig_bit =  1'b0;
else
    sdvig_bit =  sdvig_word[sdvig_num[4:0]];	
	
//cpsr_dv
always @ ( * )
if ( command_ok & command_is_dp & command[20] )
    if ( command[15:12]==4'hf )
        cpsr_dv_in =  spsr[7];
    else if ( (command[24:21]==4'd2)|(command[24:21]==4'd3)|(command[24:21]==4'd4)|(command[24:21]==4'd5)|(command[24:21]==4'd6)|(command[24:21]==4'd7)|(command[24:21]==4'd10)|(command[24:21]==4'd11) )
	    cpsr_dv_in =  bit_ov;	
    else
        cpsr_dv_in =  cpsr_dv;
else if ( command_ok & command_is_zagru_m & zagru_m_change & (summa_m==5'b0) )
    cpsr_dv_in =  spsr[7];
else if ( command_ok & command_is_msr & ~command[22] & command[19] )
    cpsr_dv_in =  vtoroy_operd[28];
else
    cpsr_dv_in =  cpsr_dv;	
	
always @ ( posedge clk or posedge rst )
if ( rst )
    cpsr_dv <= #`dil 1'd0;
else if ( cpu_en )
    cpsr_dv <= #`dil  cpsr_dv_in;
else;	
	
	

always @ ( posedge clk or posedge rst )
if ( rst )
    fiq_flag <= #`dil 1'd0;
else if ( cpu_en )
    if ( fiq )
	    fiq_flag <= #`dil  1'b1;
	else if ( command_flag )
	    fiq_flag <= #`dil  1'b0;
	else;
else;


assign fiq_en =  fiq_flag & command_flag & ~cpsr_df;


always @ ( posedge clk or posedge rst )
if ( rst )
    irq_flag <= #`dil 1'd0;
else if ( cpu_en )
    if ( irq )
	    irq_flag <= #`dil  1'b1;
	else if ( command_flag )
	    irq_flag <= #`dil  1'b0;
	else;
else;

assign irq_en =  irq_flag & command_flag & ~cpsr_di;	


always @ ( posedge clk or posedge rst )
if ( rst )
    cd_abort <= #`dil 1'd0;
else if ( cpu_en & ~derzhat_en )
	cd_abort <= #`dil  rom_abort;
else;


always @ ( posedge clk or posedge rst )
if ( rst )
    cd_und <= #`dil 1'd0;
else if ( cpu_en & ~derzhat_en )
	cd_und <= #`dil  ~all_cd;
else;


always @ ( posedge clk or posedge rst )
if ( rst )
    command_is_swi <= #`dil 1'd0;
else if ( cpu_en & ~derzhat_en )
    command_is_swi <= #`dil  cd_is_swi;
else;

assign int_all =  cpu_restart|ram_abort|fiq_en|irq_en|( command_flag & ( cd_abort|cd_und|(cond_satisfy & command_is_swi)));
	
//cpsr_di	
always @ ( posedge clk or posedge rst )
if ( rst )
    cpsr_di <= #`dil 1'd0;
else if ( cpu_en )
    if ( int_all )
        cpsr_di <= #`dil  1;
    else if ( command_ok & ( cpsr_dm != 5'b10000 ) )
        if ( ( command_is_dp &  command[20] & ( command[15:12]==4'hf ) ) |(command_is_zagru_m & zagru_m_change & (summa_m==5'b0) ) )
            cpsr_di <= #`dil  spsr[6];	
        else if ( command_is_msr & ~command[22] & command[16]  )
            cpsr_di <= #`dil  vtoroy_operd[7];
        else;
    else;
else;

//cpsr_df
always @ ( posedge clk or posedge rst )
if ( rst )
    cpsr_df <= #`dil 1'd0;
else if ( cpu_en )
    if ( cpu_restart | fiq_en ) 
        cpsr_df <= #`dil  1;
    else if ( command_ok & ( cpsr_dm != 5'b10000 ) )
        if ( ( command_is_dp &  command[20] & ( command[15:12]==4'hf ) ) | (command_is_zagru_m & zagru_m_change & (summa_m==5'b0) ) )
            cpsr_df <= #`dil  spsr[5];        
		else if ( command_is_msr &  ~command[22] & command[16]  )
            cpsr_df <= #`dil  vtoroy_operd[6];
        else;
    else;
else;


always @ ( posedge clk or posedge rst )
if ( rst )
    cpsr_dm <= #`dil 5'b10011;
else if ( cpu_en )
    if ( cpu_restart )
        cpsr_dm <= #`dil  5'b10011;
    else if ( fiq_en )
        cpsr_dm <= #`dil  5'b10001;
    else if ( ram_abort )
        cpsr_dm <= #`dil  5'b10111;
    else if ( irq_en )
        cpsr_dm <= #`dil  5'b10010;
    else if ( command_flag & cd_abort )
        cpsr_dm <= #`dil  5'b10111;
    else if ( command_flag & cd_und )
        cpsr_dm <= #`dil  5'b11011;
    else if ( command_flag & cond_satisfy & command_is_swi )
        cpsr_dm <= #`dil  5'b10011; 
    else if ( command_ok & ( cpsr_dm != 5'b10000 ) )
        if ( ( command_is_dp &  command[20] & ( command[15:12]==4'hf ) ) |(command_is_zagru_m & zagru_m_change & (summa_m==5'b0) ) )
            cpsr_dm <= #`dil  spsr[4:0];
		else if ( command_is_msr & ~command[22] & command[16]  )
            cpsr_dm <= #`dil  vtoroy_operd[4:0];
        else;
    else;
else;   


always @ ( posedge clk or posedge rst )
if ( rst )
    m_after <= #`dil 5'b10011;
else if ( cpu_en )
    m_after <= #`dil  cpsr_dm;
else;  	

assign cpsr =  { cpsr_dn,cpsr_dz,cpsr_dc,cpsr_dv,cpsr_di,cpsr_df,cpsr_dm};	


always @ ( * )
if ( cpsr_dm == 5'b10011 )
    spsr = spsr_svc;
else if ( cpsr_dm == 5'b10111 )
    spsr = spsr_abt; 
else if ( cpsr_dm == 5'b10010 )
    spsr = spsr_irq;
else if ( cpsr_dm == 5'b10001 )
    spsr = spsr_fiq;
else if ( cpsr_dm == 5'b11011 )
    spsr = spsr_und;
else
    spsr = cpsr; 

always @ ( posedge clk or posedge rst )
if ( rst )
    spsr_und <= #`dil 11'd0;
else if ( cpu_en )
    if ( ~ram_abort & ~fiq_en & ~irq_en & ( command_flag & ~cd_abort & cd_und ) )
	    spsr_und <= #`dil  cpsr;
    else if ( command_ok & ( cpsr_dm==5'b11011) & command_is_msr & command[22] )
        spsr_und <= #`dil  {{command[19]?vtoroy_operd[31:28]:spsr_und[10:7]},{command[16]?{vtoroy_operd[7:6],vtoroy_operd[4:0]}:spsr_und[6:0]}}; 	
    else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    command <= #`dil 32'd0;
else if ( cpu_en )
    if ( ~derzhat_en )
	    command <= #`dil  cd;
    else if ( command_is_zagru_m ) begin
	    command[0] <= #`dil 1'b0;
		command[1] <= #`dil command[0] ? command[1] : 1'b0;
		command[2] <= #`dil (|(command[1:0])) ? command[2] : 1'b0;
		command[3] <= #`dil (|(command[2:0])) ? command[3] : 1'b0;		
		command[4] <= #`dil (|(command[3:0])) ? command[4] : 1'b0;
		command[5] <= #`dil (|(command[4:0])) ? command[5] : 1'b0;	
		command[6] <= #`dil (|(command[5:0])) ? command[6] : 1'b0;
		command[7] <= #`dil (|(command[6:0])) ? command[7] : 1'b0;		
		command[8] <= #`dil (|(command[7:0])) ? command[8] : 1'b0;
		command[9] <= #`dil (|(command[8:0])) ? command[9] : 1'b0;	
		command[10] <= #`dil (|(command[9:0])) ? command[10] : 1'b0;	
		command[11] <= #`dil (|(command[10:0])) ? command[11] : 1'b0;	    
		command[12] <= #`dil (|(command[11:0])) ? command[12] : 1'b0;	 
		command[13] <= #`dil (|(command[12:0])) ? command[13] : 1'b0;	
		command[14] <= #`dil (|(command[13:0])) ? command[14] : 1'b0;	 
		command[15] <= #`dil (|(command[14:0])) ? command[15] : 1'b0;	 		
        end	
	else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    spsr_svc <= #`dil 11'd0;
else if ( cpu_en )
    if ( ~ram_abort & ~fiq_en & ~irq_en & ( command_flag & ~cd_abort & ~cd_und & (cond_satisfy & command_is_swi) ) )
	    spsr_svc <= #`dil  cpsr;
    else if ( command_ok & ( cpsr_dm==5'b10011) & command_is_msr & command[22] )
        spsr_svc <= #`dil  {{command[19]?vtoroy_operd[31:28]:spsr_svc[10:7]},{command[16]?{vtoroy_operd[7:6],vtoroy_operd[4:0]}:spsr_svc[6:0]}}; 	
    else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    spsr_abt <= #`dil 11'd0;
else if ( cpu_en )
    if ( ram_abort | ( ~fiq_en & ~irq_en & ( command_flag & cd_abort ) ) )
	    spsr_abt <= #`dil  cpsr;
    else if ( command_ok & ( cpsr_dm==5'b10111) & command_is_msr & command[22] )
        spsr_abt <= #`dil  {{command[19]?vtoroy_operd[31:28]:spsr_abt[10:7]},{command[16]?{vtoroy_operd[7:6],vtoroy_operd[4:0]}:spsr_abt[6:0]}}; 	
    else;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    spsr_irq <= #`dil 11'd0;
else if ( cpu_en )
    if ( ~ram_abort & ~fiq_en & irq_en )
	    spsr_irq <= #`dil  cpsr;
    else if ( command_ok & ( cpsr_dm==5'b10010) & command_is_msr & command[22] )
        spsr_irq <= #`dil  {{command[19]?vtoroy_operd[31:28]:spsr_irq[10:7]},{command[16]?{vtoroy_operd[7:6],vtoroy_operd[4:0]}:spsr_irq[6:0]}}; 	
    else;
else;	
	
always @ ( posedge clk or posedge rst )
if ( rst )
    spsr_fiq <= #`dil 11'd0;
else if ( cpu_en )
    if ( fiq_en )
         if ( ram_abort )
            spsr_fiq <= #`dil  {cpsr_dn,cpsr_dc,cpsr_dz,cpsr_dv,1'b1,cpsr_df,5'b10111};
        else 
            spsr_fiq <= #`dil  cpsr;
    else if ( command_ok & ( cpsr_dm==5'b11011) & command_is_msr & command[22] )
        spsr_fiq <= #`dil  {{command[19]?vtoroy_operd[31:28]:spsr_fiq[10:7]},{command[16]?{vtoroy_operd[7:6],vtoroy_operd[4:0]}:spsr_fiq[6:0]}}; 	
    else;
else;		


always @ ( posedge clk or posedge rst )
if ( rst )
    cd_flag <= #`dil 1'd0;
else if ( cpu_en )
    if ( int_all | to_rf_deystvit | cha_rf_deystvit | go_rf_deystvit | zagru_m_rf_deystvit )
	    cd_flag <= #`dil  0;
	else
	    cd_flag <= #`dil  1;
else;


always @ ( posedge clk or posedge rst )
if ( rst )
    command_flag <= #`dil 1'd0;
else if ( cpu_en )
    if ( int_all )
	    command_flag <= #`dil  0;
	else if ( ~derzhat_en )
	    if ( wait_en | to_rf_deystvit | cha_rf_deystvit | go_rf_deystvit | zagru_m_rf_deystvit )
		    command_flag <= #`dil  0;
		else
		    command_flag <= #`dil  cd_flag;
	else;
else;





assign cd_rm_deystvit =  cd_is_msr0|cd_is_dp0|cd_is_bx|cd_is_dp1|cd_is_mult|cd_is_multl|cd_is_swp|cd_is_ldrh0|cd_is_ldrsb0|cd_is_ldrsh0|cd_is_ldr1;

assign cd_rm_num =  cd[3:0];

assign cd_rs_deystvit =  cd_is_dp1|cd_is_mult|cd_is_multl;	

assign cd_rs_num =  cd[11:8];

assign cd_rn_deystvit =  cd_is_dp0|cd_is_dp1|cd_is_swp|cd_is_ldrh0|cd_is_ldrh1|cd_is_ldrsb0|cd_is_ldrsb1|cd_is_ldrsh0|cd_is_ldrsh1|cd_is_dp2|cd_is_ldr0|cd_is_ldr1|cd_is_zagru_m;

assign cd_rn_num =  cd[19:16];

assign cd_rnhi_deystvit =  ((cd_is_ldrh0|cd_is_ldrh1|cd_is_ldr0|cd_is_ldr1)& ~cd[20]);

assign cd_rnhi_num =  cd[15:12];


assign wait_en =  cd_flag&( (cha_deystvit&( (cd_rm_deystvit&(cha_num==cd_rm_num))|(cd_rs_deystvit&(cha_num==cd_rs_num))|(cd_rn_deystvit&(cha_num==cd_rn_num))|(cd_rnhi_deystvit&(cha_num==cd_rnhi_num)) )) | (go_deystvit&( (cd_rm_deystvit&(go_n==cd_rm_num))|(cd_rs_deystvit&(go_n==cd_rs_num))|(cd_rn_deystvit&(go_n==cd_rn_num)) )) | (to_deystvit&( (cd_rm_deystvit&(to_n==cd_rm_num))|(cd_rs_deystvit&(to_n==cd_rs_num))|(cd_rn_deystvit&(to_n==cd_rn_num)) )) | (zagru_m_deystvit & (summa_m==5'b0)&( (cd_rm_deystvit&(zagru_m_num==cd_rm_num))|(cd_rs_deystvit&(zagru_m_num==cd_rs_num))|(cd_rn_deystvit&(zagru_m_num==cd_rn_num)) )) | (cpsr_dm!=m_after) );


always @ ( * )
case ( command[31:28] )
4'h0 : cond_satisfy =  ( cpsr_dz==1'b1 );
4'h1 : cond_satisfy =  ( cpsr_dz==1'b0 );
4'h2 : cond_satisfy =  ( cpsr_dc==1'b1 );
4'h3 : cond_satisfy =  ( cpsr_dc==1'b0 );
4'h4 : cond_satisfy =  ( cpsr_dn==1'b1 );
4'h5 : cond_satisfy =  ( cpsr_dn==1'b0 );
4'h6 : cond_satisfy =  ( cpsr_dv==1'b1 );
4'h7 : cond_satisfy =  ( cpsr_dv==1'b0 );
4'h8 : cond_satisfy =  ( cpsr_dc==1'b1 )&(cpsr_dz==1'b0);
4'h9 : cond_satisfy =  ( cpsr_dc==1'b0 )|(cpsr_dz==1'b1);
4'ha : cond_satisfy =  ( cpsr_dn==cpsr_dv);
4'hb : cond_satisfy =  ( cpsr_dn!=cpsr_dv);
4'hc : cond_satisfy =  ( cpsr_dz==1'b0)&(cpsr_dn==cpsr_dv);
4'hd : cond_satisfy =  ( cpsr_dz==1'b1)|(cpsr_dn!=cpsr_dv);
4'he : cond_satisfy =  1'b1;
4'hf : cond_satisfy =  1'b0;
endcase

assign reg_rm =  sdvig_word;


always @ ( posedge clk or posedge rst )
if ( rst )
    reg_rs <= #`dil 32'd0;
else if ( cpu_en )
    if ( ~derzhat_en )
        if ( cd_is_multl & cd[22] & cd_rs[31] )
	        reg_rs <= #`dil  ~cd_rs + 1'b1;
		else
		    reg_rs <= #`dil  cd_rs;
	else if ( command_is_mult | ( command_is_multl & ( summa_m==5'b10 ) ) )
	    reg_rs <= #`dil  mult_ans[31:0];
	else if ( command_is_multl & ( summa_m==5'b1 ) )
	    reg_rs <= #`dil  reg_rm;
	else;
else;


assign mult_ans =  reg_rm * reg_rs;


always @ ( posedge clk or posedge rst )
if ( rst )
    command_is_mult <= #`dil 1'd0;
else if ( cpu_en & ~derzhat_en )
    command_is_mult <= #`dil  cd_is_mult;
else;

always @ ( posedge clk or posedge rst )
if ( rst )
    command_is_multl <= #`dil 1'd0;
else if ( cpu_en & ~derzhat_en )
    command_is_multl <= #`dil  cd_is_multl;
else;


always @ ( posedge clk or posedge rst )
if ( rst )
    multl_extra_num <= #`dil 1'd0;
else if ( cpu_en & command_is_multl & ( summa_m==5'b1 ) )
    multl_extra_num <= #`dil  bit_cy;
else;



assign derzhat_en =  command_ok & ( command_is_swp | ( (command_is_zagru_m|command_is_mult|command_is_multl) & (summa_m !=5'b0) ) );	


assign command_ok =  ~int_all & command_flag & cond_satisfy;	



always @ ( posedge clk or posedge rst )
if ( rst )
    command_is_b <= #`dil 1'd0;
else if ( cpu_en & ~derzhat_en )
    command_is_b <= #`dil  cd_is_b;
else;


always @ ( posedge clk or posedge rst )
if ( rst )
    command_is_bx <= #`dil 1'd0;
else if ( cpu_en & ~derzhat_en )
    command_is_bx <= #`dil  cd_is_bx;
else;	


always @ ( posedge clk or posedge rst )
if ( rst )
    rf <= #`dil 32'd0;
else if ( cpu_en )
    if ( cpu_restart )
	    rf <= #`dil  32'h0000_0000;
	else if ( fiq_en )
	    rf <= #`dil  32'h0000_001c;
	else if ( ram_abort )
	    rf <= #`dil  32'h0000_0010;
	else if ( irq_en )
	    rf <= #`dil  32'h0000_0018;
	else if ( command_flag & cd_abort )
	    rf <= #`dil  32'h0000_000c; 
	else if ( command_flag & cd_und )
	    rf <= #`dil  32'h0000_0004;
    else if ( command_flag & cond_satisfy & command_is_swi )
        rf <= #`dil  32'h0000_0008;
	else if ( zagru_m_deystvit & (zagru_m_num==4'hf ) )
        rf <= #`dil  zagru_m_data;	
	else if ( go_deystvit & (go_n==4'hf) )
        rf <= #`dil  go_data;
    else if ( command_ok & command_is_dp & ( command[24:23]!=2'b10 ) & ( command[15:12]==4'hf ) )
	    rf <= #`dil  dp_vykhod;	
	else if ( command_ok & command_is_b )
	    rf <= #`dil  summa_rn_rm;
	else if ( command_ok & command_is_bx )
	    rf <= #`dil  sdvig_word;
    else if ( ~derzhat_en & ~wait_en )
        rf <= #`dil  rf + 3'd4;
    else;
else;


always @ ( posedge clk or posedge rst )
if ( rst )
    rfx <= #`dil 32'd0;
else if ( cpu_en & ~derzhat_en & ~wait_en )
    rfx <= #`dil  rf + 4'd8;
else;


assign rf_b =  rf - 3'd4;	

assign to_rf_deystvit =  command_ok & ( ( (command[15:12]==4'hf) & ( command_is_dp & ( command[24:23]!=2'b10 ) ) ) |  command_is_b | command_is_bx ); 


assign rom_en =  cpu_en & ( ~(int_all | to_rf_deystvit | cha_rf_deystvit | go_rf_deystvit | zagru_m_rf_deystvit | wait_en | derzhat_en ) );

assign rom_addr =  rf;	





endmodule
